1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a method of characterizing and improving a masking process by comparing an actual pattern produced with a masking process to a computerized image designed to estimate the pattern.
2. Description of the Related Art
Photolithographic and etch processes (collectively referred to as masking processes) are universally employed in semiconductor processing to fabricate patterns necessary to produce the various levels of a semiconductor process. In a typical photolithographic process, a photoresist layer is deposited upon a semiconductor substrate and exposed to an energy source in the presence of a patterned photo mask placed between the energy source and the photoresist layer. The patterned photo mask includes transparent and opaque areas for selectively exposing regions of a photoresist layer. Exposing portions of the photoresist layer alters the solubility of the exposed portions so that a subsequent developer step can selectively remove portions of the photoresist layer to produce a desired pattern. In a positive masking process, the initial photoresist layer is insoluble in the developer solution and the portions of the photoresist layer that are subsequently exposed to the energy source become soluble in the developer solution. In a negative resist process, the initial photoresist layer is soluble in the developer solution and the portions of the photoresist layer exposed to the energy source are altered to become insoluble. Thus, in a positive resist process, the patterned image remaining after the develop step comprises the unexposed portions of the photoresist layer while, in a negative resist process, the exposed portions remain after develop. Regardless of the type of photoresist used, the photolithography process is typically followed by an etch process during which the photoresist (pr) pattern is transferred to the underlying substrate by etching away the portions of the underlying substrate not covered or masked by the pr pattern. Etch processes for various substrate materials including doped and undoped silicon, doped and undoped silicon dioxide, silicon nitride, and various metal and refractive metals including aluminum, copper, tungsten, titanium, molybdenum, and alloys thereof are well known in the field of integrated circuit fabrication.
Ideally, the pr pattern produced by the photolithography process and the substrate pattern produced by the subsequent etch process would precisely duplicate the pattern on the photomask. For a variety of reasons, however, the pr pattern remaining after the resist develop step may vary from the pattern of the photomask significantly. Diffraction effects and variations in the photolithography process parameters typically result in critical dimension (CD) variation from line to line depending upon the line pitch (where pitch is defined for purposes of this disclosure as the displacement between an adjacent pair of interconnect lines). In addition to CD variation, fringing effects and other process variations can result in end-of-line effects (in which the terminal end of an interconnect line in the pattern is shortened or cut off by the photolithography process) and corner rounding (in which square angles in the photomask translate into rounded corners in the pattern). These three primary optical proximity effects, together with other photoresist phenomena such as notching, combine to undesirably produce a patterned photoresist layer that may vary significantly from the pattern of the photomask. In addition to variations introduced during the photolithography process, further variations and distortions are typically introduced during the subsequent etch process such that the pattern produced in the semiconductor substrate may vary from the photomask pattern even more than the pr pattern.
Conventional semiconductor process engineering in the areas of photolithography and etch typically includes controllably altering the process parameters associated with the various masking steps in an attempt to obtain a finished pattern that approximates the desired pattern as closely as possible. Among the parameters process engineers typically attempt to vary in an effort to produce a pr pattern substantially identical to the photomask pattern include the intensity, coherency and wave length of the energy source, the type of photoresist, the temperature at which the photoresist is heated prior to exposure (pre-bake), the dose (intensity x time) of the exposing energy, the numerical aperture (NA) of the lens used in the optical aligner, the use of antireflective coatings (ARC), the develop time, developer concentration, developer temperature, developer agitation method, post bake temperature, and a variety of other parameters associated with the photolithography process. Etch parameters subject to variation may include, for example, process pressure and temperature, concentration and composition of the etch species, and the application of a radio frequency energy field within the etch chamber. Despite their best efforts, however, semiconductor process engineers are typically unable to manipulate the photolithography and etch processes such that the photoresist and substrate patterns produced by the processes are substantially identical to the photomask pattern.
In an effort to compensate for the discrepancies between the pr pattern and the photo mask, optical proximity correction (OPC) techniques have been employed. In a typical optical proximity correction technique, features of a photomask pattern are distorted in an effort to anticipate various process effects to produce a final pr pattern that resembles the desired pattern. Because diffraction and other effects typically result in shrinking or rounding of lines and corners, the distortions typically take on the appearance of appendages to the extremities of the various features of a photomask pattern. While OPC techniques have been useful in improving the final appearance of pr patterns, OPC typically requires numerous iterations to produce a desired result. The cost associated with semiconductor photolithography processing equipment substantially precludes the dedication of a particular piece of equipment to experimentation necessary to characterize and optimize each photolithography mask and process.
To avoid the time and cost of producing actual test wafers for every desired permutation of process parameters, computerized simulation of masking processes is employed to facilitate the optimization of a particular masking sequence and the generation of an OPC distorted photomask. Masking process simulators receive various inputs corresponding to the parameters of the photoresist and etch processes to be simulated and attempt to simulate the pattern that will be produced by the specified masking process given a particular photomask. Process simulation also enables relatively inexpensive and quick comparison of various OPC techniques. Accordingly, computerized has significantly enhanced the process engineer's ability to characterize and optimize masking processes.
Nevertheless it is typically impossible to adequately account for the multitude of parameters associated with a masking process despite the enormous effort devoted to masking process characterization, the introduction of optical proximity correction techniques, and the emergence of sophisticated process simulation software. In other words, simulation programs are ultimately unable to account for the various parametric dependencies in a manner sufficient to predict the exact pattern that will be produced by any particular masking process and mask. Because it is desirable to be able to substantially produce a desired pattern in a masking process, it would be extremely beneficial to provide a method for improving the simulation software to accurately predict the final pattern produced by a masking process based upon actual results obtained using the masking process.